Bringing Agile To Quantum Hardware

IBM Quantum operates in a way unlike most computer hardware developers: we are researching and developing a new kind of computing system while simultaneously bringing it to market. We want to build the best, highest-performance quantum computers, all while making processors available to clients so that they can experiment with quantum and find potential benefits to their organizations. Achieving this goal requires a new way of thinking about hardware development methodology.

We’ve gathered a lot of experience in order to apply agile principles to hardware development, ever since we put our first five-qubit quantum processor on the cloud in 2016. Since then, we’ve developed our 27-qubit Falcon, 65-qubit Hummingbird, and 127-qubit Eagle families of processors — and are now following along our roadmap to launch our 433-qubit Osprey by the end of this year, and the 1,121-qubit Condor by the end of 2023. All the while, we’re pushing the boundaries on Quantum Volume and CLOPS, advancing error correction, and finding meaningful demonstrations of Quantum Advantage: when quantum computers are either cheaper, faster, or more accurate than classical computers at the same relevant task.Quantum Advantage.

This journey has taught our team that we must experiment with new ideas, toss the ones that don’t work, implement the ones that do work, and integrate them all into the stable devices that we offer our clients — all at the same time. We’re excited to present the results of this agile hardware methodology and more at this year’s APS March Meeting, the largest physics conference in the world — and give insight into how this methodology works, below.

Agile hardware development to advance metrics in parallel

Improving performance attributes in parallel on multiple revisions is key to the success of our development methodology. Especially for superconducting qubits, progress on each performance metric: number of qubits, coherence times, and Quantum Volume, often occur asynchronously. Scaling typically comes first, since scaling requires many more processing steps and materials than simply building larger chips. At the same time, a smaller chip released at the same time may incorporate state-of-the-art features devoted to delivering high coherence, and features we then incorporate into a larger chip. We’re working to advance as fast as possible — and doing so means finding a way to make improvements iteratively over multiple revisions, rather than attempting to improve every facet on each new chip we build.

Take our Falcon family of 27-qubit processors as an example. Initially, our smaller test devices had the better coherence times. However, over the next couple of years, we transferred these improvements to our Falcon devices. We did not wait to scale to larger chips until all coherence details were understood — we worked on scale and coherence time separately and in parallel. We will continue to see leapfrogging of coherence and scaling technologies as we continue along our roadmap.

We will continue to see leapfrogging of coherence and scaling technologies as we continue along our roadmap.

So, what does this process look like in practice? At the highest level sit our birds: Falcon, Hummingbird, Eagle and soon Osprey.

Each of these birds also comes with a revision number. So, last year, we released Eagle r1, the first iteration of our Eagle chip. Meanwhile, we’ve had a lot more time to experiment with and improve the performance of Falcon; our most recent version is Falcon r10. Each revision typically features a major change to the chip; Hummingbird r2 has a different qubit layout than Hummingbird r1, for example, while Falcon r4 introduced readout multiplexing — the ability to measure multiple qubits with a single readout line.

Higher numbers don’t necessarily imply an immediately higher-performing device. In some cases, we’re experimenting with tradeoffs in order to maximize performance, and in other cases, we’re testing new components. Lessons learned from Falcon r6 might not be applicable for Falcon r9. Eventually, we reach points-of-no-return, decisions fundamental enough that it’s no longer worth maintaining certain revisions.

Combining engineering with research for the future of quantum

Given all of our experimenting, we can’t just focus on building better chips — we also must engineer processes to standardize chip production, while validating which devices meet a standard of performance in scale, quality, and speed. Behind this agile hardware development process are advanced semiconductor fabrication tools that allow us to quickly design masks, deposit, pattern, and etch materials onto substrate wafers.

We leverage agile practices to incorporate relevant technology elements into earlier families where there is a potential performance benefit. The hardware goes through several stages of vetting to verify yield and performance prior to deploying into the system. We don’t expect every chip to meet the performance characteristics we might expect, so it’s paramount that we also engineer a screening practice to efficiently select only the best devices to move forward. We set a high bar for our understanding and characterization of the chips so that we feel confident putting our stamp of approval on its abilities.

Those chips that consistently and repeatably pass a bar of validation we call our core systems. We also realize that many clients would like access to the most cutting-edge technology before they reach core qualification; these are our exploratory systems. It’s important to us that we allow the entire community of quantum computing researchers access to study the behavior of exploratory systems, especially our processors with larger qubit counts.

It’s been exciting for us to see the progress that our team has made, taking huge strides not only in hardware and design, but also in software and community. We feel that we’ve developed a process that will allow us to lead the way into the future as we march along our hardware and development roadmaps — roadmaps that we plan to extend far into the future.

We’re eager to use the APS March meeting and other venues to share this progress with the quantum community, overall, and hope you’ll check out some of the talks that show off how we’re using agile hardware development to build the best quantum processors.

Developing an entirely new kind of computer processor certainly isn’t easy. We’re proud to see our team leading the way to realize quantum computing.

Check out all IBM Research presentations at the 2022 APS March Meeting.